1. Field of the Invention
The present invention relates generally to testing of integrated circuits (IC) and more particularly to arithmetic built-in self-test (ABIST) of multiple scan-based ICs.
2. Background Information
Many ICs are produced in large volume and very often operate at high speeds. Since their manufacturing yield strongly depends on the silicon area, and their performance is directly related to the delays on critical paths, it is essential that the testing strategy provides a high fault coverage without a significant area overhead and performance degradation. As the costs associated with detecting faults rise over thousands of times from the time ICs are fabricated to the time the final product is released to customers, the most effective way to prevent costly rework is to consider testing issues as early in the design cycle as possible. Practical importance of this problem in conjunction with the increasing complexity of VLSI circuits not balanced by a corresponding increase in the number of input and output pins, has made built-in self-test (BIST) one of the most important technology in IC testing that is expected to profoundly influence the area requirement of ICs in upcoming years.
In BIST, the original circuit designed to perform the system functions is appended with additional circuitry for generation of test patterns1 and compaction of test responses. Thus, the BIST approach can be applied at all levels of testing, starting from wafer and device to system and field testing. Appending these circuitry to the original circuit satisfies the high fault coverage requirement while reducing the dependence on expensive external testing equipment. However, this solution compromises an IC's area and performance as it inevitably introduces either a hardware overhead or additional delays and increased latency. These delays may be excessive for high-speed ICs used in several applications such as high-performance microprocessors, digital signal processing (DSP) systems, new generations of floating point processors, and others. Therefore, BIST schemes are often evaluated on the basis of the fault coverage they provide, area overhead they require, and the performance penalty they produce. Other criteria include test application time, scalability, and test-pattern portability. For further description of BIST, see, for example, V. D. Agrawal, C. R. Kime, and K. K. Saluja, “A Tutorial on Built-In Self Test. Part 1: Principles”, IEEE Design and Test of Computers, March 1993, pp. 73-82, and V. D. Agrawal, C. R. Kime, and K. K. Saluja, “A Tutorial on Built-In Self-Test. Part 2: Applications”, IEEE Design and Test of Computers, June 1993, pp. 69-73.
1 For the purpose of this patent application, a test pattern is a set of one or more test vectors (also referred to as test cubes). 
High fault coverage in BIST can be achieved only if all faults of interest are detected, and their effects are retained in the final compacted signature. A number of test pattern generation and test response compaction techniques have been proposed in the open literature and are used in the industrial practice. The majority of these techniques employ Linear Feedback Shift Registers (LFSRs), Multiple Input Signature Registers (MISRs), or Cellular Automata (CAs), as implementation platforms to cope with various types of failures and errors, and to support variety of test scenarios.
An efficient test pattern generator which guarantees complete fault coverage while minimizing test application time, area overhead, and test data storage is clearly essential for a successful BIST scheme. The generation schemes proposed in the art so far offer trade-offs between these parameters. The solutions range from pseudo-random techniques that do not use any storage (for test data) but take a long application time and often do not detect some faults to deterministic techniques that may require significant storage but achieve complete fault coverage in a relatively short time. Since most of the traditional design for testability (DFT) techniques use internal and external scan paths, several test pattern generators for incorporating into these designs have been also employed. They differ in the requirements placed on the nature of produced test vectors and on the scan-path features they utilize. A common drawback of the scan-path techniques is a long test application time due to the need to scan data in and out of the circuit. This usually alleviated by breaking the scan chain (also referred to as the scan register) into many shorter paths which are loaded in parallel from the generator, and scanned out in parallel to a signature generator. Consequently, a number of techniques have been proposed in the art for two-dimensional test-sequence generation. They are mostly based on LFSRs as shown for example by W. J. Hurd in the paper entitled “Efficient Generation of Statistically Good Pseudonoise by Linearly Interconnected Shift Resisters”, IEEE Trans. Computers, vol. C-23, 1974, pp. 146-152, and, due to structural and linear dependencies, may not be able to produce some test patterns.
In general, schemes based on pseudo-random patterns may fail to detect some faults in some circuits due to inherent limitations of pseudo-random test vectors. In such a case, deterministic patterns are used to target the remaining hard-to-test faults. Using these deterministic patterns in conjunction with the pseudo-random patterns allows obtaining different trade-offs between test data storage and test application time by varying the relative number of deterministic and pseudo-random patterns. However, the overall efficiency of BIST scheme resting on such mixed-mode generation techniques strongly depends on the methods employed to reduce the amount of test data.
The quantity of test data can be reduced by compressing deterministic test patterns. This approach rests on the fact that the deterministic test patterns frequently feature a large number of unspecified positions. A compression method based on the reseeding of LFSRs has been originally proposed by B. Koenemann in the paper entitled “LFSR-Coded Test Patterns for Scan Designs”, in Proc European Test Conf., Munich 1991, pp. 237-242. A comprehensive analysis of this scheme as well as a new reseeding scenario based an Multiple Polynomial Linear Feedback Shift Registers (MP-LFSRs) has been provided by S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois in the paper entitled “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers”, IEEE Trans. on Computers, vol. C-44, February 1995, pp. 223-33. A similar technique has been also discussed by S. Hellebrand, B. Reeb, S. Tarnick, and H.-J. Wunderlich in the paper entitled “Pattern Generation for a Deterministic BIST Scheme”, in Proc. ICCAD, November 1995, pp. 88-94. Using this method, a concatenated group of test cubes with a total of s specified bits is encoded with approximately s bits specifying a seed and a polynomial identifier. The content of the MP-LFSR is loaded for each group, and has to be preserved during the decompression of each test cube within the group. An alternative to concatenation was proposed by N. Zacharia, J. Rajski, and J. Tyszer in the paper entitled “Decompression of Test Data using Variable-Length Seed LFSRs”, Proc. VLSI Test Symposium, Princeton 1995, pp.426-33. The underlying idea rests on the concept of variable-length seeds. Deterministic patterns are generated by an LFSR loaded with the seeds whose lengths may be smaller than the size of the LFSR. Allowing such “shorter” seeds yields higher encoding efficiency even for test cubes with varying number of specified positions.
Efficiency of the test response compaction techniques, in common with the test generation schemes, is another essential factor for a successful BIST scheme. Many schemes have been proposed to compact test responses in the conventional BIST environments. The best-known compaction techniques are based on LFSRs, CAs, counters and check sums. Extensive theoretical studies have been conducted to analyze both the asymptotic and transient behavior of the aliasing probability (i.e., the average probability of no faults being detected due to compaction after a sufficiently long test experiment) introduced by these schemes. The most commonly used compactors for compaction of parallel responses in the multiple scan environments are based on the MISRs. They introduce the aliasing probability of 2−n, where n is the size of the register, and their transient behaviors depend on the characteristic polynomials. A systematic review of the compaction schemes and related theoretical results is provided by S. Pilarski and T. Kameda in A Probabilistic analysis of test-response compaction, IEEE Computer Society Press, 1995.
Circuits based on data-path architectures constitute an increasingly large portion of integrated chips manufactured by the microelectronics industry. The proliferation of embedded cores and high-performance computing systems, such as DSP circuits, micro-controllers, and micro-processors clearly demonstrates inadequacy of existing BIST schemes if they are to entail non-intrusive, at-speed and portable testing. Recently, a new BIST paradigm was proposed by S. Adham, M. Kassab, N. Mukherjee, K. Radecka, J. Rajski, and J. Tyszer in the paper entitled “Arithmetic built-in self-test for digital signal processing architectures”, Proc. CICC, pp. 659-662, 1995, which makes it possible to use the functionality of these circuits (also referred to as mission logic or mission data paths) to perform built-in self-test for a DSP core rather than adding test hardware which can introduce area overhead and performance degradation. The resulting test sessions are controlled by microcode and use the mission data path building blocks, such as adders, multipliers, and ALUs, to generate test patterns for a DSP core, and compact its test responses. In such an environment, the need for extra hardware is either entirely eliminated or drastically reduced, test vectors are easily distributed to different parts of the DSP core, test responses are easily collected, and there is virtually no performance degradation. Furthermore, the approach can be used for at-speed testing, thereby providing a capability to detect failures that may not be detected by conventional low-speed testing. However, the ABIST proposal presented in the Adham article did not address generation of test patterns for peripheral devices, in particular, peripheral devices with “shortened” multiple scan-chains in ICs.
Thus, it is desirable to be able to extend the ABIST methodology to provide efficient BIST methods for multiple scan-based ICs, and tailoring the ABIST to conventional DFT environmental.